The integration of multiple chips into a single package has been a major trend in the semiconductor industry in order to reduce the volume and cost of consumer products. So far, many multi-chip packaging methods have been introduced and used in real products.
As the density of chips has increased, chip packaging itself has been changed significantly in terms of size and pin counts. According to the high density of memory chip and small form-factor issues, MCPs (Multi Chip Packages) are a good solution to make any system more compact. So far, the majority of chip stacking has been done with wire bonding technology. However, it requires as much space as conventional bonding pads on each chip to be connected by bonding wires.
In order to make MCPs, a more complicated lead-frame is required. Also, each chip should be disposed to have enough spacing, which results in a form factor increase. Bonding wire technology can also reduce the mechanical durability of the MCP from the wires being at odd angles.
In addition, wire bonding requires spacers for each chip. This results in increased height of the stack, which makes the handling and the assembly of the integrated device stack more challenging compared to stacks that do not comprise spacers. Also, the length of the bond wires is greater in a chip stack having spacers, which leads to a reduced electrical performance of the chip stack system. Furthermore, the thermal resistance of an integrated device stack having a spacer in the integrated device chips is increased.
Conventional integrated device stacks are prone to produce electrical shorts of the bond wires while applying the spacer material and while positioning an integrated device onto the spacer material. This reduces reliability and yield of production. Conventional bonding wire based die stacking does not provide compact packaging. Large loading effects also result from the wire length and connection layout.
Another approach is to use a via between chips. The through chip via can be a better approach to resolve the issue of noise from the electrical characteristics.
FIG. 1 shows a partial top view 102 and cross-section view 104 of a conventional multi-chip stack or multi-chip device 100 made using through-chip via technology. In the top view 102, a plurality of signal pads A1-A6 and B1-B6 are shown, which facilitate connection of internal and external signals to the chip. The vias themselves are not seen in the top view. The cross section-view 104 is taken along line A-A in the top view. The through chip via method used in FIG. 1 relates to common input or output connections, or parallel connections. Because of this, the only real fabrication issue was how deeply clean holes could be drilled and made to connect the same pins to each other as a common connection. In the case of multi-drop connections among same memory chips, the alignment of each chip is so important that all chips are aligned without a pad spacer, which is required in the bonding wire connection for multi-chip packaging.
Other known approaches are directed to the use of through chip vias for parallel connections between chips. For example, United States Patent Application Publication No. US 2007/0246257-A1 describes a memory circuit in which memory chips are connected by through silicon vias in a multi drop topology. However, in this approach, the via extends through all memory chips of a stack, thus limiting the type of connectivity that can be provided.
It is, therefore, desirable to provide a multi-chip package, or stack of chips, that use through-chip vias to provide other connections for daisy chain connections to enhance signal performance.